A DC-Balanced, Partitioned-Block, 8B/10B Transmission Code

In this paper, an 8b/10b encoding serializer/deserializer (SerDes) circuit using a DC-balanced, partitioned block, 8b/10b transmission code was presented. The information format of this transmission code consists of packets which are variable in length and can be suitable for high speed applications. Serializer and deserializer blocks were designed separately. The serializer circuit gets the 8-bit data in parallel mode and delivers the 10-bit codedserialized data to deserializer and deserializer decodes the information and delivers the 8-bit parallel information. Except serializer circuit which was designed using Cadence in 0.6 μm CMOS technology, all of the blocks were designed in Verilog and VerilogXL in XILINX. Finally all of the blocks were combined together to have an integrated system. 